Interleaving of Gate Sizing and Constructive Placement for Predictable Performance

Sungjae Kim, Eugene Shragowitz, George Karypis, and Rung-Bin Lin
International Symposium on VLSI Design, Automation, and Test, pp. 1-4, 2007
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This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.
Research topics: Circuit partitioning | hMETIS