Multi-objective Circuit Partitioning for Cutsize and Path-based Delay Minimization

Cristinei Ababel, Navaratnosothie Selvakkumaran, Kia Bazargan, and George Karypis
IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 181 - 185, 2002
Download Paper
In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a new objective function that incorporates a truly path-based delay component for the most critical paths. To avoid semi-critical paths from becoming critical, the traditional slack-based delay component is also included in the cost function. The proposed timing driven partitioning algorithm is built on top of the hMetis algorithm, which is very efficient. Simulations results show that 14% average delay improvement can be obtained. Smooth trade-off between cutsize and delay is possible in our algorithm.
Research topics: Circuit partitioning | hMETIS | VLSI CAD