hMETIS - Hypergraph & Circuit Partitioning
Related research publications
-
Interleaving of Gate Sizing and Constructive Placement for Predictable Performance.
Sungjae Kim, Eugene Shragowitz, George Karypis, and Rung-Bin Lin . International Symposium on VLSI Design, Automation, and Test, pp. 1-4, 2007.
-
Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization.
Navaratnasothie Selvakkumaran and George Karypis. IEEE Transactions on CAD, 25(3), pp. 504-517, 2006.
-
Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization.
Navaratnasothie Selvakkumaran and George Karypis. IEEE/ACM International Conference on Computer Aided Design (ICCAD), 726-733, 2003.
-
Perimeter Degree: A Priori Metric for Directly Measuring and Homogenizing Interconnection Complexity in Multilevel Placement.
Navaratnasothie Selvakkumaran, Phiroze Parakh, and George Karypis. IEEE Conference on System Level Interconnect Prediction (SLIP), pp. 53 - 59, 2003.
-
Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization.
Navaratnasothie Selvakkumaran and George Karypis. Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 726-733, 2003.
-
Multi-objective Circuit Partitioning for Cutsize and Path-based Delay Minimization.
Cristinei Ababel, Navaratnosothie Selvakkumaran, Kia Bazargan, and George Karypis. IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 181 - 185, 2002.
-
Multilevel k-way Hypergraph Partitioning.
George Karypis and Vipin Kumar. VLSI Design, Vol. 11, No. 3, pp. 285 - 300, 2000.
-
Multilevel Hypergraph Partitioning: Applications in VLSI Domain.
George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. IEEE Transactions on VLSI Systems, Vol. 7, No. 1, pp. 69-79, 1999.
-
Multilevel k-way Hypergraph Partitioning.
George Karypis and Vipin Kumar. 36th Design Automation Conference, pp. 343 - 348, 1999.
-
Multilevel Hypergraph Partitioning: Applications in VLSI Domain.
George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. 34th Design and Automation Conference, pp. 526 - 529, 1997.
|
|